Peripheral Data transmission method for the dreamcast game system constructed using the maple bus

Abstract

To provide a new data transmission system between a game device and related peripheral devices, and a device using same. Serial transmission data is divided into an odd-numbered bit sequence and an even-numbered bit sequence. Each bit of the odd-numbered bit sequence data is distributed respectively between pulses of a first pulse sequence signal having a constant interval, thereby forming a first pulse sequence signal (SDCKA). Each bit of the even-numbered bit sequence data is distributed respectively between pulses of a second pulse sequence signal having a constant interval, thereby forming a second pulse sequence signal (SDCKB). The respective time axes are adjusted such that the clock component of the first pulse sequence signal is located in the data section of the second pulse sequence signal, and the clock component of the second pulse sequence signal is located in the data section of the first pulse sequence signal. Data is transmitted using these adjusted first and second pulse sequence signals (SDCKA, SDCKB).

Foreign Application Priority Data

References Cited [Referenced By]

U.S. Patent Documents

Primary Examiner: Lee; Thomas
Assistant Examiner: Peyton; Tammara
Attorney, Agent or Firm: Keating & Bennett, LLP

Claims

What is claimed is:

1. A data transmission system comprising:

a data transmitting device which is arranged to transmit data serially via a first data signal and a second data signal, said first data signal containing a first clock signal including a sequence of first pulses and odd-numbered bits of said data, the odd-numbered bits of data being arranged in the first data signal in order between the sequence of first pulses of said first clock signal;

said second data signal containing a second clock signal including a sequence of second pulses having the same frequency as said sequence of first pulses of said first clock signal and including even-numbered bits of said data, the even-numbered bits of data being arranged in order between the sequence of second pulses of said second clock signal;

the data bits in said first and second data signals being allocated such that a data bit in one of the first and second data signals is located at a timing corresponding to a clock signal component of the clock signal in the other of the first and second data signals.

2. The data transmission system according to claim 1, further comprising a data receiving device which is arranged to receive the first and second data signals and retrieve the data out of the received first and second data signals by alternately latching a potential level of one of said first and second data signals at the timing of the clock signal component of the other of said first and second data signals.

3. A data transmission system comprising:

a data transmitter which is arranged to transmit serially data bits of data by allocating the data bits of the data into a first data signal and a second data signal;

said first and second data signals being arranged to have a format including a data frame defined according to a transmission format and including a start pattern, a data pattern and an end pattern;

said start pattern having a data format wherein, while said first data signal is maintained at a predetermined value of a constant potential level, said second data signal including a first sequence of pulses is transmitted;

said data pattern having a data format that includes a sequence of clock pulses in each of said first and second data signals so that said data bits of the data alternately a successively allocated among said clock pulses being shifted relative to one another by a prescribed amount along a time axis; and

said end pattern having a data format wherein, while said second data signal is maintained at a predetermined value of a constant potential level, said first data signal including a second sequence of pulses is transmitted.

4. An information storage medium for use with a computer system which is installed in said data transmission system according to claim 3 for collecting control signals from a peripheral device, said information storage medium storing computer game software programs for causing said computer system to operate as a game device in response to control signals from a peripheral device.

5. The data transmission system according to claim 1, wherein said clock signal component is detected based on an edge of one of the pulses in said first and second clock signals.

6. A data transmission system comprising:

a data transmitter arranged to serially transmit data composed of plural data bits by allocating the data bits of the data into a first data signal and a second data signal;

said first data signal containing a first clock signal having a sequence of pulses and a first set of data bits including every other data bit of said data and arranged such that said every other data bit of said data included in said first set of data bits is allocated in order between said pulses of said first clock signal;

said second data signal containing a second clock signal having a sequence of pulses and a second set of data bits including every other data bit of said data not included in said first set of data bits and arranged such that said every other data bit of said data included in said second set of data bits is allocated in order between said pulses of said second clock signal; and

the data bits in said first and second data signals being allocated such that a data bit in one of said first and second data signals is located at a timing corresponding to a clock signal component of the clock signal in the other of said first and second data signals.

7. The data transmission system according to claim 6, further comprising a data receiver arranged to receive said first and second data signals and adapted to retrieve the data out of the received first and second data signals by alternately latching a potential level of one of said first and second data signals at the timing of the clock signal component of the other of said first and second data signals.

8. The data transmission system according to claim 6, wherein said clock signal component is detected based upon one of a rising edge and a falling edge of each pulse in said first and second clock signals.

9. A data transmission system:

a game device having a plurality of peripheral ports each arranged to send data to, and collect data from, a peripheral device, said game device executing a software program in response to data received from one of said plurality of peripheral ports;

at least one peripheral device connectable to one of said peripheral ports via a transmission path and arranged to receive data from, and send data to, said game device;

said game device and said peripheral device each including data control means for interactively transmitting data via said transmission path by converting data bits of the data to be sent into a pair of data signals each including a data frame;

one data frame of said pair of data signals including a start pattern carrying data start information, a data pattern and an end pattern carrying data end information;

said data pattern having a data format including a sequence of clock pulses in each of said pair of data signals and bits of the data being alternately allocated in order between said clock pulses in said pair of data signals, a timing of clock pulses being shifted between said sequences of clock pulses of said pair of data signals relative to each other by a period such that a data bit in one of said pair of data signals is located at a timing corresponding to a clock signal component of a clock pulse in the other of said pair of data signals;

said game device and said peripheral device each including data retrieving means for retrieving the data out of the received pair of data signals by alternately latching a potential level of one of said pair of data signals at the timing of the clock signal component of the other of said pair of data signals.

10. The data transmission system according to claim 9, wherein said start pattern has a data format such that a first of said pair of data signals transmits a first train of pulses while a second of said pair of data signals maintains a constant potential level; and

said end pattern has a data format such that a first of said pair of data signals transmits a second train of pulses while a second of said pair of data signals maintains a constant potential level.

11. A data communication system comprising:

a data generator for converting data into serial data on a time axis in a form of first and second serial data signals, the data generator converting data bits of said data by inserting the data bits between each pulse of a transmission clock pulse sequence and shifting the first and second serial data signals relative to each other by an appropriate amount on the time axis so that each pulse edge of one of the first and second serial data signals is located in a data section of the other of the first and second serial data signals.

12. The data communication system according to claim 11, further comprising a serial bus operatively connected to the data generator and receiving the first and second serial data signals from the data generator; and

a data receiver operatively connected to the serial bus and arranged to receive the first and second serial data signals from the data generator via the serial bus.

13. The data communication system according to claim 12, wherein the data receiver receives the first and second serial data signals and retrieves data out of the first and second serial data signals by alternately latching a potential level of one of the first and second serial data signals at a timing of a clock signal component of the other of the first and second serial data signals.

14. The data communication system according to claim 11, wherein said data generator includes a circuit for converting data to the first and second serial data signals, the circuit including at least one shift register, a shift clock and at least one selector.

15. The data communication system according to claim 14, wherein a plurality of even numbered bits of the data are supplied to input terminals of the at least one shift register and data is shifted by the shift clock and the shifted data is supplied from an output terminal of the at least one selector as serial data.

16. The data communication system according to claim 15, wherein a clock signal is input to the at least one selector and the at least one selector selects serial data from an output terminal of the at least one selector in accordance with a High level of the shift clock signal and selects a clock signal in accordance with a Low level of the shift clock signal.

17. The data communication system according to claim 14, wherein a plurality of odd numbered bits of the data are supplied to input terminals of the at least one shift register and data is shifted by the shift clock and the shifted data is supplied from an output terminal of the at least one selector as serial data.

18. The data communication system according to claim 17, wherein a clock signal is input to the at least one selector and the at least one selector selects serial data from an output terminal of the at least one selector in accordance with a High level of the shift clock signal and selects a clock signal in accordance with a Low level of the shift clock signal.

19. The data communication system according to claim 11, wherein serial clock data in the first and second serial data signals alternately form negative edges.

20. The data communication system according to claim 11, wherein the data receiver receives the first and second serial data signals and the data receiver latches a data section of one of the first and second serial data signals in accordance with a negative edge timing of a waveform of the other of the first and second serial data signals so that the data section is read out to produce reproduction data.

21. The data communication system according to claim 11, wherein the data receiver receives the first and second serial data signals and the data receiver latches a data section of one of the first and second serial data signals in accordance with a positive edge timing of a waveform of the other of the first and second serial data signals so that the data section is read out to produce reproduction data.

22. The data communication system according to claim 11, wherein the first and second serial data signals are generated such that falling edges of each of the first and second serial data signals always occur alternately when data is being transmitted in the other of the first and second serial data signals.

23. The data communication system according to claim 11, wherein said first and second serial data signals have a format including a data frame defined according to a transmission format and including a start pattern, a data pattern and an end pattern;

said start pattern having a data format wherein, while said first serial data signal is maintained at a constant potential level, said second serial data signal including a first sequence of pulses is transmitted;

said data pattern having a data format that includes a sequence of clock pulses in each of said first and second serial data signals including bits of data alternately and successively allocated among said clock pulses of said first and second serial data signals, said sequences of clock pulses being shifted relative to one another by a prescribed amount along a time axis; and

said end pattern having a data format wherein, while said second serial data signal is maintained at a constant potential level, said first serial data signal including a second sequence of pulses is transmitted.

24. The data communication system according to claim 23, wherein the data communication system is provided in a game device having a plurality of peripheral ports, said data pattern comprises a command and a parameter, said parameter comprises an address of one of a plurality of peripheral devices connected to the game device via the plurality of peripheral ports, an address of the peripheral port with which said one of said plurality of peripheral devices is connected and data to be transmitted from the game device to said one of said plurality of peripheral devices.

25. The data communication system according to claim 11, wherein said first serial data signal includes odd-numbered bits of said data and said second serial data signal includes even-numbered bits of said data to be transmitted to said at least one peripheral device.

Description

TECHNICAL FIELD

The present invention relates to interface technology for providing mutual connection between data processing devices, which conduct data processing, and peripheral devices, which conduct input/output of information, and the like, and more particularly, it relates to a new interface technology standard relating to connections between game devices and related peripheral devices.

BACKGROUND ART

Data transmission methods for use in data communications between the main unit of an image processing device and peripheral devices related thereto include the following. Philips, I.sup.2 C bus system

In this system, serial data and a serial clock are transmitted by two wires. The data and clock are physically separated, and data transmission/reception and reproduction are possible by the simplest method. The I.sup.2 C bus is described, or example, in Philips' I.sup.2 C bus instruction manual (January 1992). SGS--Thomson DS link system.

In this system, a data signal and strobe signals are transmitted by two wires. A clock signal is reproduced by means of the data signal and strobe signal. When the transmitted data changes to a different value, only the data signal changes. When the transmitted data is the same value, only the strobe signal changes. For example, if the transmitted data in the data signal changes from "0".fwdarw."1", or "1".fwdarw."0", then the strobe signal does not change. If the transmitted data in the data signal does not change, e.g., "0" .fwdarw."0", or "1".fwdarw."1", then the strobe signal only changes. Therefore, by adopting an exclusive-OR operation for the data signal and strobe signal, it is possible to reproduce a clock signal. The DS link system is introduced in Nikkei Electronics, Vol. 675, (Nov. 4.sup.th 1996, pp. 167-171). In consumer-oriented devices, such as game devices, it is necessary to use a data transmission system and interface connection standard which can be implemented at low cost. However, in the aforementioned I.sup.2 BUS system, since the transition edge of the data signal has the same timing as the transition edge of the clock, it is not possible to use the clock signal directly on the data reproducing (demodulating) side. Furthermore, in the latter DS link system, exclusive-OR logic is applied to the data signal and strobe signal, to reproduce a synchronizing clock. The data signal must be sampled using this clock. Therefore, the level of simplicity of the interface circuit structure does not adequately satisfy the conditions for domestic game devices, where low cost is a very important requirement.

Consequently, it is an object of the present invention to provide a data transmission system for an interface having an inexpensive circuit composition, which can be applied to an image processing device, such as a domestic game system. It is a further object of the present invention to provide a data transmission system for an interface, whereby data can be separated from a signal carrying data by means of a simple circuit composition.

It is a further object of the present invention to provide a game device and a related peripheral device comprising interfaces, whereby data can be separated from a signal carrying data by means of a simple circuit composition.

It is a further object of the present invention to provide basic technology for developing various types of peripheral devices, by proposing novel interface technology between a game device and peripheral device.

DISCLOSURE OF THE INVENTION

In order to achieve the aforementioned objects, the data transmission system according to the present invention is a data transmission system for transmitting data by distributing one item of serial data into first and second data signals, wherein the first data signal contains each of the odd-numbered bits of the serial data, respectively distributed between pulses of a first clock formed by means of a pulse sequence having a uniform interval; the second data signal contains each of the even-numbered bits of the serial data, respectively distributed between pulses of a second clock formed by means of a pulse sequence having the same frequency as the first clock signal; the first data signal is transmitted such that the pulse edge of its clock signal component is located in the data section of the second data signal on the time axis; and the second data signal is transmitted such that the pulse edge of its clock signal component is located in the data section of the first data signal on the time axis (FIG. 10, FIG. 11, FIG. 50, FIG. 54). Furthermore, in a data transmission system wherein a data frame defined according to a transmission format comprising, at the least, a start pattern carrying data start information, a data pattern carrying serial data, and an end pattern carrying data end information, are transmitted by distributing the data frame between a first and a second data signal, the data transmission system according to the present invention is a data transmission system, wherein the start pattern is created by setting the first data signal to a constant value and setting the second data signal as a first pulse sequence signal; the data pattern is created by forming the first data signal by distributing each of the odd-numbered bits of the serial data respectively between pulses of a second pulse sequence signal having a constant interval, and forming the second data signal by distributing each of the even-numbered bits of the serial data respectively between pulses of a third pulse sequence signal, which is shifted by a prescribed amount from the position on the time axis of the second pulse sequence signal; and the end pattern is created by setting the second data signal to a constant value, and setting the first data signal as a fourth pulse sequence signal. (FIG. 11, FIG. 12, FIG. 50, FIG. 54)

By means of this composition, it is possible to create a communications interface wherein the modulation and demodulation circuits can be composed relatively simply by means of a small number of data lines (namely, two data lines).

Preferably, the superimposed data is isolated by latching the level of one data signal of the first and second data signals at the pulse edge of the clock signal component of the other data signal. Thereby, it is possible to isolate the superimposed data by means of a simple circuit composition (FIG. 10, FIG. 28, FIG. 29, FIG. 50).

In a game device which requests transmission or reply of information required for a game by transmitting two data signals (SDCKA, SDCKB) simultaneously to a single or plurality of peripheral devices by means of a signal transmission path, the game device according to the present invention comprises: start pattern creating means for creating a start pattern represented by two data signals, wherein a first data signal is set to a constant value (or fixed value) state during a first time period, and a second data signal is set to a clock signal state during the first time period (FIG. 13(a), FIGS. 14, 58, 103b); data pattern creating means for creating a data pattern represented by two data signals, wherein data to be transmitted to the peripheral device is divided into two data sequences, and a first data signal is created by inserting each bit of the first data sequence respectively between pulses of a first clock signal, and a second data signal is created by inserting each bit of the second data sequence respectively between pulses of a second clock signal having the same frequency as, and a prescribed phase difference from, the first clock signal (FIGS. 10, 103b); end pattern creating means for creating an end pattern represented by two data signals, wherein the second signal is set to a constant value (or fixed value) state during a second time period, and the first signal is set to a clock signal state during the second time period (FIGS. 13, 58, 103b); and frame creating means for creating a frame represented by two data signals, containing the start pattern, the data pattern and the end pattern, and transmitting the frame as a transmission unit to the peripheral device (FIGS. 58, 103b).

Preferably, the data is serial data, the first data sequence is a data sequence comprising the odd-numbered bits of the serial data, and the second data sequence is a data sequence comprising the even-numbered bits of the serial data.

Furthermore, the prescribed phase difference is determined such that the pulse edge of the clock signal contained in one data signal of the two data signals representing the data pattern is located in the data section of the other data signal on the time axis, and the pulse edge of the clock signal contained in the other data signal is located in the data section of the aforementioned data signal on the time axis (FIGS. 10, 50).

The game device for implementing the foregoing data transmission method can readily separate out the data since either one or both of the two data signals comprises a transmission clock component. The modulation and demodulation circuit can be constructed relatively simply.

Preferably, the data pattern comprises a command and a parameter, and the parameter comprises, at the least, the address of the peripheral device connected to the signal transmission path which is to receive the frame (FIG. 7, FIG. 48). Since the signal format for data communications between the game device and peripheral device is standardized by a frame format, compatibility between the game device and a plurality of types of peripheral device can be readily guaranteed.

For the signal transmission path, wired data signal lines, or wireless radio communications channels (FIG. 95), or optical communications channels (FIG. 96), or a combination of these, can be used.

In a peripheral device for a game device which sends information required for a game to a game device having one input/output port or a plurality of input/output ports by transmitting two data signals simultaneously, the game device according to the present invention comprises:

start pattern creating means for creating a start pattern represented by two data signals, wherein a first signal is set to a constant value (or fixed value) state during a first time period, and a second signal is set to a clock signal state during the first time period; data pattern creating means for creating a data pattern represented by two data signals, wherein data to be transmitted to the game device is divided into two data sequences and each bit of the first data sequence is inserted respectively between pulses of a first clock signal, and each bit of the second data sequence is inserted respectively between pulses of a second clock signal having the same frequency as, and a prescribed phase difference from, the first clock signal; end pattern creating means for creating an end pattern represented by two data signals, wherein the second signal is set to a constant value (or fixed value) state during a second time period, and the first signal is set to a clock signal state during the second time period; and frame creating means for creating a frame represented by two data signals, containing the start pattern, the data pattern and the end pattern, and transmitting the frame as a transmission unit to the game device.

Preferably, the data is serial data which is readily divided into two data sequences, the first data sequence is a data sequence comprising the odd-numbered bits of the serial data, and the second data sequence is a data sequence comprising the even-numbered bits of the serial data. As well as serial data, block data can also be handled by means of a buffer for gathering data.

Preferably, the prescribed phase difference is determined such that the pulse edge of the clock signal contained in one data signal of the two data signals representing the data pattern is located in the data section of the other data signal on the time axis, and the pulse edge of the clock signal contained in the other data signal is located in the data section of the one data signal on the time axis (FIG. 10, FIG. 50). Thereby, it is possible readily to isolate the data superimposed on one data signal by means of the other clock.

Preferably, the data pattern comprises a command and a parameter, and the parameter comprises, at the least, the address of the input/output port of the game device which is to receive the frame (FIG. 48, FIG. 57).

Preferably, the data pattern comprises a command and a parameter, the parameter comprises, at the least, a source address indicating the address on the transmission path of the peripheral device transmitting the frame, and this source address is created on the basis of peripheral device identification information representing the type of the peripheral device already recorded by the peripheral device, and information relating to the input/output port to which the peripheral device is connected as indicated by the game device (FIG. 58).

In a peripheral device for conducting data communications with a game device comprising one input/output port or a plurality of input/output ports by means of a data transmission path connecting to one of the input/output ports of the game device, the peripheral device according to the present invention comprises: first storage means for previously storing identification information for the peripheral device representing the type of the peripheral device; second storage means for storing input/output port information representing the input/output port to which the data transmission path is connected, as indicated by the game device; and source address creating means for creating a source address for the peripheral device which is appended to the data to be transmitted to the game device, on the basis of the peripheral device identification information and the input/output port information (FIG. 58).

By means of this composition, the game device is able to identify from the received transmission data the address of the peripheral device on the data transmission path and the type of that peripheral device.

In a peripheral device for conducting data communications with a game device by means of a data transmission path connecting to any one of a single input/output port or plurality of input/output ports provided in the game device, the peripheral device according to the present invention comprises: a single base connector which connects to the data transmission path; a single expansion connector or plurality of expansion connectors which connect to the data transmission path via the base connector, in order to connect other peripheral devices to the data transmission path; and an input/output controller for conducting data communications with the game device via the base connector; wherein the input/output controller comprises: first storage means for previously storing peripheral device identification information representing the fact that the device is a peripheral device which is to be connected directly to the game device; second storage means for storing input/output port information representing the input/output port to which the data transmission path is connected, as indicated by the game device; connection identifying means for creating connection information representing the connection status of other peripheral devices by identifying whether or not a further peripheral device is connected to any of the expansion connectors; and source address creating means for creating a source address containing the peripheral device identification information, the input/output port information and the connection information, which is to be appended to the transmission data (FIG. 58).

Preferably, the identifying means determines whether or not there is a connection at the expansion sockets by identifying the voltage level of a particular terminal of the expansion connectors, which is connected to a level shift circuit composed such that a bias voltage is supplied by the further peripheral device.

In an expansion peripheral device which connects to an expansion connector of the aforementioned peripheral device, the expansion peripheral device according to the present invention comprises: first storage means for storing connector identification information representing the number of an expansion connector as indicated by the input/output controller via the expansion connector, after connecting to the expansion connector; second storage means for previously storing expansion peripheral device information representing the fact that the device is a peripheral device which is to be connected to the expansion connector; third storage means for storing input/output port information representing the input/output port to which the data transmission path is connected, as indicated by the game device by means of the data transmission path, the base connector and the expansion connector; and source address creating means for creating a source address containing the expansion peripheral device information, the input/output port information, and the connection information, which is to be appended to is transmission data (FIG. 59).

In a game device comprising a single input/output port or a plurality of input/output ports for connecting via a main data transmission path (M bus) a base peripheral device composed such that a single expansion peripheral device or a plurality of expansion peripheral devices can be connected thereto via auxiliary data transmission paths (LM bus), the game device according to the present invention comprises: an input/output controller for conducting intermittent data communications with any of the peripheral devices by means of frame signals; wherein data communications are conducted according to a format whereby a relevant peripheral device responds to instructions from the input/output controller; the frame signals comprise: a start pattern representing the start of a data pattern, a data pattern carrying transmission data, and an end pattern representing the end of a data pattern; the data pattern comprises a command and a parameter; the parameter comprises a destination address and a source address; and both the destination address and the source address are created by including information relating to the main data transmission path used in communications, the base device/expansion device classification of the peripheral device involved in communications, and the auxiliary data transmission path used in communications (FIG. 58, FIG. 59).

Preferably, the auxiliary data transmission paths are connected respectively in parallel to the main data transmission path, and direct data communications are conducted between the game device and expansion peripheral devices.

Preferably, the base peripheral devices and the expansion peripheral devices each respectively hold inherent information containing information on the type of peripheral device and information inherent to the device, and the game device reads out this inherent information by means of the data transmission. The game device can identify compatibility between the game application and the peripheral device by referring to the inherent information.

Thereby, it is possible to avoid the use of game devices which are incompatible with so-called "plug and play" systems or applications.

Preferably, the main data transmission path is constituted by two data lines, and two data signals formed by dividing the frame signal are used to transmit the two data lines, respectively. Thereby, it is possible to apply the data transmission method according to the present invention to a game device.

In a base peripheral device for a game device, to which a single expansion peripheral device or a plurality of expansion peripheral devices can be connected by means of respectively provided auxiliary data transmission paths, and which is connected to a game device comprising a single input/output port or a plurality of input/output ports by means of a main data transmission path, the base peripheral device according to the present invention comprises an input/output controller for conducting intermittent data communications with the game device by means of frame signals; and the data communications are conducted according to a format whereby the input/output controller responds to instructions from the game device; the frame signals comprise: a start pattern representing the start of a data pattern, a data pattern carrying transmission data, and an end pattern representing the end of a data pattern; the data pattern comprises a command and a parameter; the parameter comprises a destination address and a source address; and both the destination address and the source address are created by including information relating to the main data transmission path used in communications, the master/slave classification of the peripheral device involved in communications, and the auxiliary data transmission path used in communications (FIG. 58 and FIG. 59).

The base peripheral for a game device according to the present invention further comprises a connector for connecting to the main data transmission path, and a plurality of expansion connectors for connecting the main data transmission path to the auxiliary data transmission paths in parallel by means of the connector.

Preferably, the base peripheral device comprises storage means for storing inherent information including the type of peripheral device and information inherent to the device, and this inherent information is transmitted by means of the data communications in response to a request from the game device.

Preferably, the base peripheral device uses the data transmission method according to the present invention by means of a composition wherein the main data transmission path is constituted by two data lines, and two data signals formed by dividing the frame signal are used to transmit the two data lines, respectively.

By connection to a game device having a plurality of input/output ports, the peripheral device of the foregoing composition conducts data communications with the game device, and creates a source address for itself on the data transmission path by means of information relating to the input/output port as indicated by the game device, and information representing the type of peripheral device held by the device itself.

In an expansion peripheral device for a game device which connects to a game device by means of an auxiliary data transmission path, a base peripheral device to which expansion peripheral devices can be connected, and a main data transmission path, the expansion peripheral device according to the present invention comprises an input/output controller for conducting intermittent data communications with the game device by means of frame signals; and data communications are conducted according to a format whereby the input/output controller responds to instructions from the game device; the frame signals comprise: a start pattern representing the start of a data pattern, a data pattern carrying transmission data, and an end pattern representing the end of a data pattern; the data pattern comprises a command and a parameter; the parameter comprises a destination address and a source address; and both the destination address and the source address are created by including information relating to the main data transmission path used in communications, the base device/expansion device classification of the peripheral device involved in communications, and the auxiliary data transmission path used in communications (FIG. 59).

Preferably, the main data transmission path is constituted by two data lines, the auxiliary data transmission path is constituted by two data lines in the upstream direction and two data lines in the downstream direction, and two data signals formed by dividing the frame signal are used to transmit the two data lines, respectively.

The expansion peripheral device of the foregoing composition conducts data communications with a game device comprising a plurality of input/output ports by means of a peripheral device (base peripheral device) having a plurality of expansion connectors connected in parallel to any one of the input/output ports. It creates a source address used in data communications by means of information relating to the input/output port, as indicated by the game device, and information relating to the expansion connector used, as indicated by the peripheral device. The source address is not simply an address, but also contains certain information. This type of function of the peripheral device is suitable for plug and play systems, and the like.

The information storage medium according to the present invention stores programs for causing a computer system to operate as the aforementioned game device (host) or peripheral device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustrative diagram showing examples of a host (game device) 1, peripheral device 2 and expansion peripheral device 3;

FIG. 2 is a block diagram showing a host control system;

FIG. 3 is a block diagram illustrating connection relationships between a host and devices;

FIG. 4 is a block diagram illustrating relationships between a host, upper devices and lower devices;

FIG. 5 is a block diagram illustrating the allocation of absolute positions;

FIG. 6 is a block diagram illustrating that the devices have positional permeability when viewed from the host;

FIG. 7 is a diagram illustrating the composition of one frame of transfer data;

FIG. 8 is a block diagram illustrating the composition of an interface from the software side;

FIG. 9 is a block diagram illustrating transmission protocol levels between a host and device;

FIG. 10 is a diagram illustrating a data transmission system;

FIG. 11 is a diagram illustrating a standard format of a transmission frame;

FIG. 12 is a diagram illustrating a transmission frame format comprising a CRC option;

FIG. 13 is a diagram illustrating (a) a start pattern and (b) an end pattern of a synchronizing pattern;

FIG. 14 is a diagram illustrating a CRC option start pattern;

FIG. 15 is a diagram illustrating an SDCKB occupancy permission pattern;

FIG. 16 is a diagram illustrating a reset pattern;

FIG. 17 is a diagram illustrating a communications mode between a host and device function;

FIG. 18(a) is a diagram illustrating an aspect of the M bus where data communications are conducted intermittently according to a format whereby the device functions respond to commands from a host; FIG. 18(b) is a diagram illustrating an example where the data to be transmitted is long, and the data is transmitted intermittently using a plurality of transmission frames;

FIG. 19 is a diagram giving an approximate illustration of the operation of a device;

FIG. 20 is a diagram illustrating an absolute position (AP) setting procedure;

FIG. 21 is a block circuit diagram illustrating a host MIE;

FIG. 22 is a block circuit diagram illustrating the operational principles of a frame encoder;

FIG. 23 is a timing chart illustrating the operation of a frame encoder;

FIG. 24 is a block circuit diagram illustrating the operational principles of an alternate shift register;

FIG. 25 is a timing chart illustrating the operation of an alternate shift register (parallel-to-serial conversion);

FIG. 26 is a block circuit diagram illustrating the operational principles of a frame decoder;

FIG. 27 is a timing chart illustrating the operation of a frame decoder;

FIG. 28 is a block circuit diagram illustrating the operational principles of an alternate shift register (serial-to-parallel conversion);

FIG. 29 is a timing chart illustrating the operation of an alternate shift register;

FIG. 30 is a block diagram giving an approximate illustration of the general composition of a standard controller;

FIG. 31 is a block diagram illustrating a standard controller MIE;

FIG. 32 is a block diagram illustrating a bus switching section which is data-permeable (position-permeable);

FIG. 33 is a block circuit diagram illustrating a U-device MIE;

FIG. 34 is a block circuit diagram illustrating an L-device MIE;

FIG. 35 is a flowchart illustrating identification of a transmission pattern in an MIE;

FIG. 36 is a flowchart illustrating the formation of a standard format frame signal;

FIG. 37 is a flowchart illustrating formation of a frame signal of a format with CRC option;

FIG. 38 is a flowchart illustrating operation by means of an SDCKB occupancy pattern;

FIG. 39 is a flowchart illustrating transmission of a reset pattern;

FIG. 40 is a flowchart illustrating a reception operation in an MIE;

FIG. 41 is a flowchart illustrating processing in a case where a start pattern is detected;

FIG. 42 is a flowchart illustrating processing in a case where a start pattern comprising CRC is detected;

FIG. 43 is a flowchart illustrating an example where inherent information held by the device is read out by the host;

FIG. 44 is a diagram illustrating a plurality of modes for connecting a host, base devices and expansion devices;

FIG. 45 is a diagram giving a conceptual illustration of the relationship between a host and functions (base devices and expansion devices).

FIG. 46 is a diagram illustrating data communications between a host, base device and expansion device, by means of a layered model;

FIG. 47 is a diagram illustrating connection relationships between a base device and expansion devices;

FIG. 48 is a diagram illustrating the composition of frame data;

FIG. 49 is a diagram illustrating a Time Out;

FIG. 50 is a diagram illustrating data transmission by means of an SDCKA signal and SDCKB signal;

FIG. 51 is a diagram illustrating a start pattern and an end pattern;

FIG. 52 is a diagram illustrating an SDCKB occupancy permission pattern;

FIG. 53 is a diagram illustrating a reset pattern;

FIG. 54 is a diagram illustrating a frame format;

FIG. 55 is a diagram giving an approximate illustration of data transmission between a host and peripheral device (base device or expansion device);

FIG. 56(a) is a diagram illustrating how data communications are conducted intermittently by means of a format whereby devices respond to commands transmitted to the devices by the host; FIG. 56(b) is a diagram illustrating an example where data to be transmitted is divided into a plurality of data and transmitted intermittently by means of a plurality of transmission frames, when the data to be transmitted is larger than the volume that can be transmitted by a single transmission frame;

FIG. 57 is a diagram illustrating all AP values for a host, base devices and expansion devices;

FIG. 58 is a diagram illustrating an AP setting procedure (absolute address) for a base device;

FIG. 59 is a diagram illustrating an AP setting procedure (absolute address) for an expansion device;

FIG. 60 is a diagram illustrating frame data transfer between a host, base device and expansion device;

FIG. 61 is a diagram illustrating a normal communications procedure between a host and base device (or expansion device);

FIG. 62 is a diagram illustrating an SDCKB occupancy procedure between a host and base device;

FIG. 63 is a block diagram illustrating a host MIE;

FIG. 64 is a block diagram illustrating the composition of a base device;

FIG. 65 is a block diagram illustrating the composition of a base device MIE;

FIG. 66 is a block diagram illustrating a connection between a base device and an expansion device;

FIG. 67 is a diagram illustrating a procedure in a case where a base device receives data from a host;

FIG. 68 is a diagram illustrating a procedure in a case where a base device receives data of a volume larger than the transmission and reception buffer from the host;

FIG. 69 is a diagram illustrating a procedure in a case where data is transmitted from a base device to a host;

FIG. 70 is a diagram illustrating a procedure in a case where data of a volume larger than the capacity of the MIE transmission and reception buffer is transmitted from a base device to a host;

FIG. 71 is a diagram illustrating a "Device Request" command;

FIG. 72 is a diagram illustrating an "All Status Request" command;

FIG. 73 is a diagram illustrating a "Device Reset" command;

FIG. 74 is a diagram illustrating a "Device Kill" command;

FIG. 75 is a diagram illustrating a "Data Transfer" command;

FIG. 76 is a diagram illustrating a "Get Condition" command;

FIG. 77 is a diagram illustrating a "Get Media Info" command;

FIG. 78 is a diagram illustrating a "Block Read" command;

FIG. 79 is a diagram illustrating a "Block Write" command;

FIG. 80 is a diagram illustrating a "Get Last Error" command;

FIG. 81 is a block diagram showing an example of a base device (game controller) having a relative address;

FIG. 82 is a block diagram showing an example of a base device (game controller) having an absolute address;

FIG. 83 is a block diagram showing an example of an expansion device (LCD cartridge) having a relative address;

FIG. 84 is a block diagram showing an example of an expansion device (LCD cartridge) having an absolute address;

FIG. 85 is a block diagram showing an example of an expansion device (memory cartridge) having a relative address;

FIG. 86 is a block diagram showing an example of an expansion device (memory cartridge) having an absolute address;

FIG. 87 is a block diagram showing an example of an expansion device (vibrating cartridge) having a relative address;

FIG. 88 is a block diagram showing an example of an expansion device (vibrating cartridge) having an absolute address;

FIG. 89 is a block diagram showing an example of an expansion device (light gun cartridge) having a relative address;

FIG. 90 is a block diagram showing an example of an expansion device (light gun cartridge) having an absolute address;

FIG. 91 is a block diagram showing an example of an expansion device (sound input cartridge) having a relative address;

FIG. 92 is a block diagram showing an example of an expansion device (sound input cartridge) having an absolute address;

FIG. 93 is a block diagram showing an example of an expansion device (sound output cartridge) having a relative address;

FIG. 94 is a block diagram showing an example of an expansion device (sound output cartridge) having an absolute address;

FIG. 95 is a diagram illustrating an example where an M bus is constituted by a wireless system (radio);

FIG. 96 is a diagram illustrating a further example where an M bus is constituted by a wireless system (optical transmission);

FIG. 97(a) is a diagram illustrating an M bus connector of a game controller; FIG. 97(b) is a diagram illustrating an LM bus connector of a game controller;

FIGS. 98(a) and 98(b) are diagram illustrating a further example of a game controller;

FIG. 99 is a side view illustrating an example of a socket of an M bus connector;

FIG. 100(a) is a side view illustrating an M bus connector plug; FIG. 100(b) is a top view of this plug; FIG. 100(c) is a front view of this plug;

FIG. 101 is a diagram of a connector provided on the peripheral device (base device) side of an M bus cable;

FIG. 102(a) is a top view of an LM bus connector socket; FIG. 102(b) is front view of this plug;

FIG. 103(a) is a top view of an LM bus connector plug; and FIG. 103(b) is a front view of this plug.

BEST MODE FOR CARRYING OUT THE INVENTION

Summary of Composition

Firstly, an outline of the system composition is described with reference to FIG. 1 and FIG. 2. FIG. 1 is an illustrative diagram for describing a game device comprising a computer system. FIG. 2 is a block diagram for describing a control system for this game device.

The game device (host) 1 comprises: a CPU 1a for executing game programs, and the like; a ROM 1b for storing control programs, data, OS, and the like, for the game device; a CD-ROM device 1c for storing game application programs and data; a bus controller id for controlling data transfer between the CPU 1a and other sections; a RAM 1e for storing programs and data for the CPU 1a, which is used in data processing; a drawing processor 1f for generating image signals from drawing data; a sound processor 1g for forming sound signals from sound data; a peripheral interface 1h for relaying data transfer between the CPU 1a and external peripheral devices; and the like. A portion of the RAM 1e is used as a working RAM for peripheral data processing, thereby enabling a so-called DMA operation. An image signal and sound signal are supplied to a monitor 4 (e.g. TV monitor), and video images and sounds are output. The peripheral devices comprise basic peripheral devices 2 and expansion peripheral devices 3. The basic peripheral devices 2 are connected to the peripheral interface 1h via a connector 1i, and the expansion peripheral devices 3 are connected to the basic peripheral devices 2. The basic peripheral devices 2 and expansion peripheral devices 3 are connected electrically (or by logic structure) to the host in parallel. The basic peripheral devices 2 are, for example, game controllers, and the expansion peripheral devices 3 are, for example, sound input devices, sound output devices, light ray gun modules, vibrating devices, memory devices, or the like.

Here, in the first mode of implementation (first interface standard) described below, the peripheral devices are investigated in terms of the function that they perform, and they are divided into U device function and L device function. This classification takes into account the fact that, in addition to cases where a single peripheral device forms a single function, there are also cases where a plurality of functions are formed by a single peripheral device, and cases where a single function is realized by a plurality of peripheral devices.

On the other hand, in the second mode of implementation (second interface standard) described below, the peripheral devices are divided into basic peripheral devices and expansion peripheral devices according to the connection relationships between the devices.

The modes for implementing the present invention are broadly classified into a first mode of implementation and second mode of implementation.

First Mode of Implementation

Initially, the meaning of terminology used in the first interface standard according to the present invention is described with reference to the drawings.

Firstly, data obtained by expanding data on a time series is called "serial data". A signal line which exchanges data in the form of serial data is called a "serial bus". A serial bus which connects a game device and peripheral devices by means of the interface standard according to the present invention is called an M bus (M-Bus).

The registration system identification number allocated initially to the device function of each peripheral device is called the "device ID". A plurality types, for example, 256 types of device ID can be prepared. It is also possible to have a plurality of the same device numbers at a single port.

The section whereby a peripheral device can be connected to the peripheral controller of the game device via the M bus is called a "port". The M bus enables the active connection of a plurality of ports. It is, for example, possible to support 16 ports, but this mode of implementation relates to an example where four ports (port A, port B, port C, port D) are supported.

As shown in FIG. 3, the game device is called the "host", and one function of a peripheral device connected thereto is called a "device function". Since "device function" indicates a function of a device, rather than the device (product) itself, in addition to cases where a single function is realized by a single device, it is also possible to divide the function of a single device into a plurality of functions, each of which is taken as a device function. On the M bus, there is one host device, which is connected to device functions in a tree configuration. Each device function appears as though it is present on the same M bus. A plurality of device functions, for example, 14 device functions, can be connected to a single port. The device functions allow the peripheral devices of the game device to function as, for example, a game controller, game pad, joystick, keyboard, imitation control device, imitation gun, recording device, sound device, and the like.

As shown in FIG. 4, the device functions are divided into two types: "upper (U) device function" and "lower (L) device function". The U-device functions can be connected to the host. The U-device functions have the capacity to control L-device functions. The L-device functions are based on the premise that they are connected, (or can connect) with a U-device function. An M bus which links an L-device function to a U-device function is called an "LM bus".

Unless at least one U-device function is provided at a port, that port cannot be used. Principally, game device controllers form U-device functions, and expansion (peripheral connected) devices form L-device functions. The M bus can be connected, for example, to a maximum of 14 L-device functions.

Furthermore, it is possible to connect a U-device function to a U-device function. In this case, the connected U-device function becomes an L-device function. It is unnecessary for the U-device functions and L-device functions to be separated physically, and it is possible for a further device function separated logically within a U-device function to form an L-device function.

For example, within the device function-controlling IC (e.g., microcomputer or micro-controller) of the peripheral device, the digital control sections and the analogue control sections can be set by function as U-device functions and L-device functions, respectively, and when an analogue control section, namely, an L-device function, is not in use, it is possible to disable that section.

As FIG. 5 shows, numbers are allocated to each device function in order from port A, such that any one of plurality of device functions can be accessed directly by the host at each port of the host. The identification number (or symbol) for access allocated to each device function is called the "absolute position (AP)".

On the M bus, a plurality of device functions are allocated to a single port of the host. The relationship between the number of ports on the M bus and the number of APs is expressed by the following equation:

(Maximum number of ports).times.(Maximum number of APs allocated to one port)=constant

In the M bus according to the mode of implementation, the "constant" is taken to represent one byte. In this case, (4 ports (max. 16 ports)).times.(APs for max. number of ports)=1 byte.

Of the 16 APs, one AP is reserved for the host port, so there is a maximum of 15 APs allocated to any single port. Therefore, a maximum of 15 device functions can be used at a port. Moreover, since one U-device function is connected to a port, the maximum number of L-device functions at any port will be 14. The number range that can be used at a port is determined for each port by the APs allocated to the device functions. For example, the AP will be composed as follows:

Bit 76543210

AP pppp - - - -

Here, "pppp" is the port number (port A="0000", port B="0001", port C="0010", port D="0011"), and "- - - -" is the serial number ("0000" (denary of "0")-"1111" (denary of "15")). Accordingly, the APs for a maximum of device functions is fifteen, and fifteen device functions can be set at one port.

Indicated in binary values, the AP value of the device function is "00000001"-"00001111" at port A, "00010001"-"00011111" at port B, "00100001"-"00101111" at port C, and "00110001"-"001111111" at port D.

Indicated in denary values, the above values are 1-15, 17-31, 33-47, 49-63, and in hexadecimal values, #01-#0F, #11-#1F, #21-#2F, and #31-#3F.

The AP of each port of the host viewed from the device function is always the smallest AP value usable at that port, and at port A, it is #00, at port B, it is #10 (16), at port C, it is #20 (32), and at port D, it is #30 (48). The device function and host can identify the port to which it is connected by the leading four bits of the AP. Access to a device function specifies a device function which is accessed by this AP.

As designating an AP allocated to each device function is at the same time the designation of a device function, the host can access each device function of the peripheral device directly. Therefore, as shown in FIG. 6, viewed from the host, the host appears to be connected to each device function directly. In other words, each device appears to be connected to the same bus.

The data exchange between host and device function is not conducted by conventional one-way communications, but rather by using certain specific instructions, such that data appropriate to that time and place can be transmitted and received. These instructions are called "commands". The command data is called a "parameter".

One cycle of transmission data is constituted by one frame (e.g., 256 bytes) comprising a command+parameter, as shown in FIG. 7. The parameter may include AP data, data size, and data, or data may be omitted.

In principle, the host accesses a device function by issuing a command. When the device function has prepared the corresponding data, it issues a command to the host and sends the data. On the M bus, a maximum of 254 commands, for example, can be prepared, and a maximum of 253 bytes of data can be transmitted.

A location for connecting an expansion device for expanding the functions of the peripheral device, such as a game controller functioning as a game operating input device, is called an "expansion socket." In principle, L-devices are connected to expansion sockets. A standard game controller may comprise two expansion sockets, for example. The M bus may be provided with an equal number of expansion sockets to the number of L-device functions, for instance, 14 in the case of this mode of implementation.

A circuit which converts certain data to serial data for the M bus, such that it can be communicated via the M bus, is called an "M bus I/F engine" (MIE)". M bus standard devices all comprise MIEs of this kind. The host incorporates a host MIE, the U-device functions, a U-device function MIE, and the L-device functions, an L-device function MIE.

As shown in FIG. 8, in order for the host to access a device function, it is always necessary to operate via software (M bus driver) which exercises general control over the device functions. The device functions are controlled and managed by the M bus driver. This M bus driver manages the device ID (function identification number), AP (absolute position), and port, etc., and it controls and manages the reception and transmission of commands, the data format, and the like. Commands can be increased by improving (upgrading) and augmenting the M bus driver.

On the M bus, all device functions are obliged to have information particular to themselves (inherent information) recorded according to a prescribed format. This device function information is called "device status".

The device status records the product name, device ID, licence, model number, destination, LM bus number, and the like, as management data, and the standby current consumption and maximum current consumption, etc., as electrical data (hardware information). The device status is managed and utilized by the M bus driver and application program interface (API); for example, it enables the product name and connection capacity of a peripheral device to be identified, and allows the current for all ports to be controlled, on the basis of the maximum current consumption, and the like.

FIG. 9 gives an approximate illustration of the proposed scope of the present interface standard. The application software performed in the host conducts the data communication with the device functions in the peripheral devices via the software called API, or directly by giving instructions to the M bus driver. Commands formed by the M bus driver in accordance with the instructions are supplied via the host MIE, cable, peripheral device MIE, and MIE controller to control software, which forms the nucleus of the device functions of the peripheral device. This control software sends a reply corresponding to the command in question to the application software performed in the host, via the MIE controller, peripheral device MIE, cable, host MIE, and M bus driver. It is possible to provide a plurality of device functions in a peripheral device, and in this case, it is possible for each device function to share use of an MIE. Here, the MIEs and connecting cables, etc. represent physical levels, and the M bus driver and MIE controller represent logic levels.

Next, data transmission on the M bus will be described. On the M bus, data transmission is carried out by a synchronized serial system. The connecting cables comprise a total of four lines: a power line pair (Vcc, GND), and a data line pair (SDCKA, SDCKB: two-way). If necessary, a shield wire for shielding the connecting cable in order to prevent noise is added. Data transmission and reception uses a two-way communications half-duplex system, which is set to an appropriate data transfer speed, for example, 2 Mbps.

The principles of data transmission are now described with reference to FIG. 10. Data is transmitted by means of a serial data clock (SDCK)A and serial data clock (SDCK)B, which propagate a data line. When transmitting data, the serial data clocks A and B comprise a clock component, and they alternately form a negative edge (falling edge), as shown in FIG. 10. In other words, as shown in the data pattern section shown in FIG. 11, data bits are inserted between each pulse of the transmission clock pulse sequence, and the serial data clocks A and B are shifted relatively to each other by an appropriate amount on the time axis (a time shift whereby the pulse edge of one signal is positioned in the data section of the other signal). On the receiving side, the data section of one signal is latched in accordance with the negative edge timing of the waveform of the other signal, and this data section is read out to produce data (reproduction data). The data is transferred starting from the most significant bit (MSB), for example. A circuit for carrying out data transmission in this way can be constructed relatively simply. Moreover, the data latch timing may also be based on the positive edge (rising edge) of the signal.

According to this system, it is possible to lower the transmission frequency in a data transmission path, compared to an I.sup.2 BUS or DS-link system. For example, in order to transmit at a data transfer speed of 10 Mbit/s using an I.sup.2 BUS or DS-link system, it is necessary to operate the data transfer medium at 10 MHz. However, using the present system, since 10 Mbit of data is transmitted by dividing it between two data lines which carry 5 Mbit each, theoretically, it is possible to obtain a data transfer rate of 10 Mbit/s using a 5 MHz data transfer clock on the data lines. Furthermore, since the pulse width is lengthened by the insertion of data between the clock pulses, in the corresponding sections, the transmission frequency falls by an equivalent amount. Since a lower transmission speed is satisfactory, circuit design is simplified.

FIG. 11 and FIG. 12 show examples of signal transmission formats. A transmission format comprises: a start pattern, data pattern, and end pattern, and if necessary, CRC (Cyclic Redundancy Check) bits are added.

FIG. 11 shows a standard transmission format. Data transmission is conducted in frame units (smallest unit). The composition of one frame in the standard format begins with a start pattern (START), which indicates the start of data transmission, and then comprises a 256-byte-long data pattern (DATA), and an end pattern (END). The "D" symbols shown in the data pattern represent sections carrying the "0" and "1" bit information of the data.

FIG. 12 shows an example of a format which incorporates the CRC option, wherein an error correction function is added to the standard data format. A cyclic redundancy check (CRC), for example, may be used as an error correction method. In data transmission using a CRC option, a CRC code pattern is added after the data which is the object of the CRC, as illustrated in the data pattern in FIG. 12.

The portions outside the data pattern in the transmission format described above form information patterns which carry specific information. The information patterns are defined by the number of signal pulses (transmission clocks) for which either of the data lines SDCKA or SDCKB propagate the other signal line whilst in an "L" level state. Information patterns may include, for example, synchronizing patterns, data line occupancy permission patterns, reset patterns, and the like. Synchronizing patterns include: start patterns as illustrated in FIG. 13(a), end patterns as illustrated in FIG. 13(b), and start patterns with CRC option as illustrated in FIG. 14.

A start pattern is a synchronizing pattern transmitted prior to the aforementioned data pattern. If the MIE on the receiver side detects four negative edges of data line SDCKB whilst the data line SDCKA is at level "L", the subsequent pattern is read as a data pattern and buffered using a memory. The end pattern indicates the end of the data pattern. If the MIE on the receiver side detects two negative edges of data line SDCKA whilst the data line SDCKB is at level "L", then this confirms that the data pattern has ended and indicates proper completion of the process.

The start pattern with CRC option represents the START pattern when a CRC option is added. If the MIE on the receiver side detects six negative edges of the SDCKB line whilst the data line SDCKA is at level "L", then it is identified as data transmission comprising a CRC option. Error inspection is conducted with respect to the data section, using the 16 bits prior to the END pattern as CRC data.

FIG. 15 shows an example of a data line occupancy permission pattern whereby the host permits the receiver side to occupy one of the data lines. In an occupancy permission pattern relating to occupancy of data line SDCKB, the SDCKB line has 8 negative edges whilst SDCKA is at level "L". When the MIE on the receiver side detects the SDCKB occupancy permission pattern, then it is possible to occupy SDCKB whilst SDCKA is at "L", starting from the subsequent negative edge of SDCKA. The occupancy of SDCKB is cancelled by the following positive edge of SDCKA.

For example, it is possible to send output data from a light gun used in a shooting game device to the game device by occupying the data line SDCKB. Data is transferred by using only the data line SDCKB, and data line SDCKA indicates the occupancy time (period).

FIG. 16 shows a reset pattern. The reset pattern comprises 14 negative edges of data line SDCKB whilst data line SDCKA is at level "L". When the MIE on the receiver side detects the reset pattern, it identifies this as a reset request from the host. The device then initializes the MIE and erases the AP. No data apart from this is initialized.

Next, the transmission protocol in data communications between host and device is described with reference to FIG. 17.

Firstly, in principle, the host has the right of priority to transmit commands. Communications are conducted in a form whereby a corresponding device function responds to a command from the host. Therefore, all transmission protocols start with transmission of a command from the host. FIG. 18(a) gives an illustration of this. Data is transmitted from the host to the device function when the need arises. Therefore, on the M bus and LM bus, intermittent data communication is carried out between the host and a plurality of device functions. If the data to be transmitted exceeds the prescribed length for one transmission frame, then the data is divided into a plurality of sections as shown in FIG. 18(b), and each of the divided data sections is transmitted by a plurality of transmission frames (see FIG. 70 described below).

The host application program accesses the bus driver in order to obtain data from the device function of a particular peripheral device. The driver creates an AP, forming an address, and a command, and the MIE sends frame data carrying the AP and command to the M bus. In a normal state, the device functions connected to the bus are at standby awaiting a command from the host. The MIE at the peripheral device receives the frame data, and transfers the command to the control program of the device function via the MIE controller.

If the control program detects its own AP, it sends back a response to the relevant command via the MIE controller. The MIE creates frame data containing the return command and the host AP, and outputs this to the bus. The host receives this frame data, thereby obtaining a response to the transmitted command. The device function returns to a command standby state.

In this way, the host can obtain required information from a device function.

Next, an overview of the processing implemented in the device functions is described with reference to FIG. 19. When a power line is connected to the peripheral device and power is supplied, the device function executes an initialization process for setting initial hardware values, and the like. Thereupon, an AP setting process is implemented to set the AP value of the device function. In the AP setting process, the connected device functions are identified, and APs are allocated to the device functions, etc. By giving the device function an AP, it is possible to conduct communications between the host and device function using the AP, thus realizing a normal operational state.

In a normal operational state, when a device function receives a reset command from the host, the AP is reset (software reset). When a bus reset command is received, all the device functions connected to the bus at the corresponding port are initialized, and the APs are reset (hardware reset). The host can also order an operation to be prohibited or suspended, by transmitting a command to each device function.

The process of AP setting in the device functions is now described with reference to FIG. 20.

(1) After completing initialization, the host transmits a Device Request in sequence starting from port A, to confirm whether any device functions are connected to the ports. The Device Request is a command which requires any device function which has not been allocated an AP to send back its Device Status, which gives the information inherent to the device. It is transmitted in sequence starting from port A and ending at port D.

(2) After completing initialization, a U-device function disconnects the LM bus from the M bus and waits for a Device Request from the host. If it receives a Device Request from the host, it sends back a Device Status to the host in response. At this stage, there is only one device function at a port receiving a device request at any one time. There is no response from device functions which have not been allocated an AP.

(3) When the host receives a Device Status from a device function, it determines the connection relationship and device attributes on the basis of this data, and it allocates an AP to the device function and transmits an AP Assign carrying the allocated AP value to the device function. APs are allocated consecutively within a set range for each port, and the host detects the relationship between the AP and device function. If the device function attributes are not those expected by the applicational software (outside range of use), then the operation of that device function can be terminated by sending a Device Kill command. If the device function is a U-device function, then the L-device functions connected thereto are also terminated, thereby allowing the whole port to be disabled.

(4) The device function reads in the AP Assign from the host, stores its allocated AP, and then transmits a Device Reply to the host as a response from the device function. Thereafter, the host accesses the device function using the device ID and AP. (5) Since the host detects the number of device function LM buses currently set from the device status, if there is an LM bus, the host will transmit LM-Bus Connect such that one of the LM buses connects to a device function. If there is no LM-Bus Connect, then the processing in (10) below is implemented.

(6) When a U-device function receives LM-Bus Connect, it connects one LM bus to the M bus. It then sends a Device Reply to the host.

(7) When the host receives a Device Reply, it transmits a Device Request. In this case, since the U-device function has already been allocated an AP, it does not respond.

(8) When an L-device function receives a Device Request from the host, it sends a Device Status to the host in response.

(9) The processing from (3) to (8) is repeated until all LM buses are connected (APs are allocated to all device functions).

(10) The host sends a Function Start in order to start the operation of each device function.

(11) When the device function receives Function Start, it transfers from the AP setting operation to normal operation. After transferring, the device function sends a Device Reply to the host.

(12) Upon receiving the Device Reply, the host sends a Function Start to the next AP.

(13) Each device function is activated in sequence by repeating the processing in (11) and (12), until the device function at the final AP transmits a Device Reply, whereupon the AP setting process is completed.

(14) The device functions having transferred to normal operation, the host proceeds with AP setting for the next port.

In this way, an AP is set for each device function connected to a particular port.

Next, the processing involved when a cable is connected or disconnected whilst the host is operating (active line connection/disconnection) is described.

(1) The host transmits a Device Request to each port at prescribed intervals. Ports not in use can be excluded from the access operation.

(2) If a Device Status is transmitted from a port which was not previously connected, the host recognizes that a device function has been connected. Upon recognizing this, it outputs a reset pattern to that port, and erases the APs for all device functions. It then carries out an AP setting process to renew the APs and rebuild the connection relationships.

(3) If the host transmits a command to a device function and there is no response from the device function, the host recognizes that that device function has been disconnected. If a device function is disconnected, the host erases the APs and rebuilds the connection relationships.

Next, data transmission and reception processing during normal operation is described.

(1) Right of priority of command transmission

A command is always transmitted initially by the host, and the device functions respond to this command. If a device function initially transmits a command to the host, this is not recognized. The host does not retransmit commands unless there is a request from the device function side.

(2) Data format

The transmission and reception data is constituted by commands and parameters (AP data, data size, data). When a signal is actually transmitted along a data line, the MIE adds a start pattern and an end pattern to it, before the command and at the end of the parameters, respectively. Thereby, a single frame is constructed and transmitted in the order: "start pattern"+"command pattern"+"AP data"+"data size" +"data"+"end pattern".

The frame is analysed by the MIE of the receiving side, thereby confirming the start pattern and end pattern. The details of the commands and parameters are described later.

(3) Host

The MIE used by the host is governed by the M bus driver. Read-out of device function data is not carried out automatically by the MIE, but rather is implemented by the respective software via the M bus driver. Respective software shall herein mean software of an upper level compared to the M bus driver, for example, library software or game software. In a single access operation, it is possible to communicate with one device function having the specified AP. In order to read in data from a plurality of device functions in 1 INT, the corresponding number of device functions are accessed. 1 INT (interrupt) is a timing unit of the TV screen rewriting, namely approximately 1/60 seconds. The port connection check transmits a Device Request to unconnected ports, and if there is a reply, that port is set to "connected". When not transmitting, a port is always set to input (reception) mode. The type of command to be used differs according to the device function and the time and circumstances, so it is set according to the device function specification.

(4) Device functions

The MIEs for peripheral devices are controlled via an MIE controller by the CPU, or the like, which executes the device function programs. The device functions maintain a reception state until a command is transmitted by the host. The device functions then generate their own data necessary for communications. Furthermore, asynchronously to the access from the host, the device functions create data to be output as the function of that particular device (e.g., operation input device such as a control pad or joystick). If there is a request from the host, the data is transmitted within a prescribed period of time. The host transmits the same command to all device functions connected to the same port. The device functions analyze the received command and parameters, and send back a command only if this matches their own AP. If it does not match their own AP, they must not respond to the host. The type of command used differs according to the device function, and the time and circumstances, so the details thereof are determined according to the device function specification.

(5) Prohibited operations

Direct access from one device function to another device function connected to the same port is prohibited. Communication between device functions must be conducted via the host. Furthermore, commands which can only be issued by the host must not be used.

Exceptional processing will now be described. Exceptional processing is special processing prepared for devices wherein data transmission and reception cannot be controlled by commands. An example of such a device is a light gun used in a shooting game.

(1) If the host recognizes that the device function has a light gun device ID, then it switches the M bus from normal mode to SDCKB occupancy mode. Mode switching is not possible from the device function side. Prior to switching, the host transmits a mode change, and after confirming that a light gun is connected, it switches the M bus mode to SDCKB occupancy pattern.

Upon entering SDCKB occupancy mode, all devices at that port assume SDCKB occupancy mode, and device functions other that those operating in SDCKB occupancy mode do not receive commands. For example, if a light gun, memory card and vibrating unit are connected to port A, the device function operating in the SDCKB occupancy mode is only the light gun. During the occupancy mode, only the light gun is controlled by the host, and the other device functions, namely the memory card and vibrating unit, do not operate (cannot be controlled by the host).

(2) To return from SDCKB occupancy mode, the host carries out cancellation processing. When the SDCKB occupancy mode is terminated, the system immediately returns to normal mode.

(3) In the case of a light gun, the time period for screen rewriting in 1 INT omitting the vertical blanking period, in other words, the time period for drawing the TV screen, forms the SDCKB occupancy mode.

When the period of drawing the screen is finished and the blanking period has started, the system switches directly to normal mode, and data transmission and data reception is conducted for the device functions at other ports.

(4) In order to achieve a light gun function, a section containing a photoreceptor element is taken as one device function, and sections containing a trigger and direction keys, analogue keys, and the like, are taken as a further device function. In this way, it is possible to eliminate conventional problems, such as disabling of the direction keys when the light gun is used. Furthermore, since the light gun forms a single device function unit, it can be connected to other expansion devices. By this means, it is possible to provide game applications having new functions.

Next, examples of commands are described. Commands can be divided broadly into control commands and error commands. Control commands comprise the basic commands of: Device Request, Status Request, All Status Request, AP Assign, LM-Bus Connect, Function Start, Host Data Transmit, Data Request, All Data Request, Mode Change, Device Sleep, Device Request, Device Kill, Device Status, Device Reply, Device Data Transmit, and the like. In addition, there are expansion commands which do not belong to these basic commands. Expansion commands differ according to the device function and M bus driver.

Device Request is a command from the host requesting a device function which does not have an AP allocated to send back a Device Status.

Status Request is a command from the host requesting a device function specified by an AP to send back a Device Status (this data is inherent device information (Fixed Device Status)).

All Status Request is a command from the host requesting all device status (namely, both Fixed Device Status and Free Device Status) from a device function specified by an AP. The device function sends back the Fixed Device Status followed by the Free Device Status by means of Device Data Transmit.

AP Assign is a command whereby the host allocates an AP to a device function. It can only be executed during the AP setting process. If the device function is in normal operation, it does not process the command but sends back a Command Refusal.

LM-Bus Connect is a command from the host requesting a device function to connect one LM-Bus to the M Bus. Upon receiving LM-Bus Connect, the device functions connect the LM-Bus pertaining to them, one bus for each function. If a device function is in normal operation, it does not process the command, but sends back a Command Refusal.

Function Start is a command from the host causing a device function specified by its AP to start normal operation. If the device function receives this command and starts normal operation, it sends back a Device Reply. No initialization takes place. If the device function is in normal operation, it does not process the command, but sends back a Command Refusal.

Host Data Transmit is a command whereby the host transmits data to a device function. The data contents differ depending on the device function. The details of this data are determined by the device function specification. If the data size is 0, then the device function does not receive and it sends back a Command Refusal. During AP setting also, the device function does not receive and sends back a Command Refusal.

Data Request is a command from the host requesting a device function to transmit specified data. A plurality of request data numbers can be specified in the data region. If the data size is 00h, then the device function does not process the command and sends back a Command Refusal. During AP setting also, the device function does not process the command and sends back a Command Refusal.

All Data Request is a command from the host requesting a device function to transmit all its data. During the AP setting process, the device function does not receive the command and sends back a Command Refusal.

Mode Change is a command whereby the host switches the mode of the port M bus. When switching to SDCKB occupancy mode, after a Mode Change command has been issued, the Device Reply is confirmed and the specified port is switched to SDCKB occupancy mode. If the device function does not correspond to the operations in SDCKB occupancy mode, then it does not process the mode change and sends back a Command Refusal. During the AP setting process also, the device function does not process Mode Change, but sends back a Command Refusal.

Device Sleep is a command whereby the host temporarily suspends a specified device. When a device function has been suspended, it sends back a Device Reply and thereafter can only receive Function Start. During the AP setting process, the device function does not process Device Sleep, but sends back a Command Refusal.

Device Reset is a command whereby the host applies a software reset to a specified device function to initialize it. Software reset is not a resetting (initializing) which uses hardware functions such as IC reset terminals, but is for example the initializing of internal RAMs or registers on programs (software). As software reset enables the selection of portions to be reset in the program, it is possible to retain portions, such as the set state of the IC terminal, for which initialization is not desired. AP values which have already been allocated are not initialized. After initialization, the device function sends back a Device Reply and starts normal operation. During AP setting, the device function does not process Device Reset, but sends back a Command Refusal.

Device Kill is a command whereby the host forbids the operation of a device function. The device function can only process this command before AP Assign in the AP setting sequence. The device function waits at standby current consumption, and cannot receive any commands. In order to activate the device function, the hardware must be reset or the power turned off. Hard reset is conducted by resetting (initializing) using hardware functions such as IC reset terminals. It is also possible to conduct an equal initialization processing in the program. This processing is equal to the power on reset at the start of power supply which performs IC initialization at the same time. In contrast to the soft reset, no selection of the portion to be initialized is possible. If the device function is in normal operation, it will not process this command, but send back a Command Refusal. To suspend a device function temporarily during normal operation, the Device Sleep command is used.

Device Status is a command whereby a device function sends a Fixed Device Status to the host. This Fixed Device Status is described later.

Device Reply has a wide range of use as a device function reply transmitted by a device function. The AP in the data contents indicates the device function's own AP, thereby specifying the source of the Device Reply.

Device Data Transmit is a command whereby a device function transmits data in accordance with a request from the host. The data contents differ depending on the device function. If th e data size is 00h (h indicates hexadecimal notation), the host will not process the command, but will send back a Command Refusal. Depending on circumstances, a command such as a retransmission, Device Status, or the like, may be issued.

Next, the error commands will be described. Error commands comprise basic commands, such as Command Refusal, Command Unknown, Transmit Again, LM-Bus Error, Device Error, and the like. In addition to this, there are also expansion commands, which are intrinsic to the device function and M bus driver. Intrinsic commands herein do not mean standard commands held by the driver but commands prepared for specific device functions.

Command Refusal is a command whereby the host or device function refuses to receive data corresponding to an incoming command. This command is also transmitted if a command which is incompatible with the host or function's operation is received. This command prohibits improper access.

Command Unknown is a command transmitted from a device function to the host when the device function receives a command from the host which it does not recognize.

Transmit Again is a command sent by the host or a device function requesting the same data to be transmitted once again, when there has been an error of some kind in the data received.

LM-Bus Error is a command from a device function to the host giving notification that an error has occurred in the LM bus. This command is sent to the host in cases where, for instance, LM-Bus Connect is received from the host, but there is no LM bus to connect.

Device Error is a command from a device function notifying the host that an error of some kind has occurred in the device function and that the device function is in the process of resetting.

The Device Status information mentioned above will now be described. The Device Status stores data directly such that it cannot be rewritten or erased. For example, it is not permitted to calculate a certain value to give a status value or text.

The Device Status comprises: Fixed Device Status and Free Device Status.

Fixed Device Status relates to a permanent device status which is an essential description of the device, e.g., total 108-byte format. Unless all items are described, operation and connection of the device cannot be guaranteed.

The Free Device Status relates to a device status which can be used freely depending on the individual device function. For example, the capacity must be 148 bytes or less.

Fixed Device Status comprises the following items:

(1) Device ID

This describes the ID and attributes of the device function. By previously registering and assigning an ID to each device function, the host is able to identify what type of device function is connected by reading its ID. Therefore, those used by the M bus are registered by product in advance for those having an M bus license.

(2) Maximum data size

This describes the maximum size of data output by the device function.

(3) Number of LM buses

This describes the number of LM buses held by the device function.

(4) Product name

The product name is described in English or romaji using ASCII code. This may be different from the actual commercial name. The product name is also subject to prior registration.

(5) Destination code

This describes the region of sale of the product. For example, North America, Europe, Japan, etc. This code makes it possible to determine compatibility between peripheral devices and game applications for particular target regions.

(6) Licence

This shows the product licence in English or romaji using ASCII code.

(7) Standby current consumption

This describes the current consumed during temporary suspension, in units of 0.1 mA.

(8) Maximum current consumption

This describes the maximum current consumed, in units of 0.1 mA.

On the other hand, Free Device Status relates to areas of information which can be set freely by the product planners, developers, designers, programmers, or the like. The host can obtain this information from a device function by means of the All Device Request command. When this information region is used in application software, and the like, it is necessary to ensure compatibility of data sequences, etc. in advance.

The MIE of the host shall be specifically called a peripheral controller. FIG. 21 shows an example of a block circuit diagram for a peripheral controller (MIE) provided at the host.

In this diagram, a clock divider 51 creates a clock for supplying to each processing block of the controller from a system clock, and by varying the frequency ratio of the supplied clock, it is possible to alter the transmission (transfer) rate, and the like.

Instruction register 52 is a 32-bit register into which instructions sent from the application etc. to the peripheral devices are written via the main bus. The contents written to this register are transferred to a port controller 57 and frame controller 58.

Write buffer 53 is a 256-byte RAM into which data for transfer is written. Interrupt controller 54 is a controller for controlling interrupts due to transmission, reception, or errors of different kinds.

Status register 55 is a 32-bit register indicating the status of the main controller. Read buffer 56 is a 256-byte RAM for holding received data.

Port controller 57 is a controller for controlling ports involved in data transmission and reception. By controlling a three-state buffer 68 of a transmission port selected by a command, outputs SDCKA and SDCKB of a first and a second selector 64 and 65 are directed to the selected port. A reception port is selected by controlling a third and a fourth selector 66 and 67.

Frame controller 58 is a controller for controlling frame composition in terms of output pattern, data length, and the like.

Frame encoder 59 is controlled by the frame controller 58 and it generates and outputs information patterns.

Alternate shift register 60 is controlled by the frame controller, and it is a register for (P/S) converting parallel data in the write buffer to serial data, and alternately outputting data and a clock to SDCKA and SDCKB. A CRC calculating section is provided within the alternate shift register, and CRC processing is applied to the data in accordance with commands from the frame controller.

The first selector 64 is controlled by the frame controller 58, and it outputs SDCKA by selecting the outputs of the frame encoder 59 or the output of the alternate shift register 60.

The second selector 65 is controlled by the frame controller 58, and it outputs SDCKB by selecting the output of the alternate shift register 60 or the output of the frame encoder 59.

The third selector 66 selects a reception port in accordance with commands from the port controller 57, and it supplies SDCKA received via a buffer amp 69 to a frame decoder 61 and alternate shift register 62.

The fourth selector 67 selects a reception port in accordance with commands from the port controller 57, and it supplies SDCKB received via a buffer amp 69 to a frame decoder 61 and alternate shift register 62.

Frame decoder 61 analyzes the composition of received frames, reflects this in the Status Register 55, and controls alternate shift register 62.

Alternate shift register 62 is controlled by the frame decoder 61, and is an (S/P) register for converting received serial data to parallel data. The alternate shift register 62 also comprises a CRC calculating circuit for carrying out error inspection of the received signal.

The HV latch signal controller is activated by the frame controller 58. For example, when the frame controller 58 has transmitted an SDCKB occupancy permission pattern, the frame decoder is deactivated and the HV latch signal controller is activated. When the HV latch signal controller receives SDCKB after an SDCKB occupancy permission pattern has been transmitted, a latch signal is supplied to an HV counter (omitted from drawing). The HV counter comprises a horizontal position counter and vertical position counter, which output values corresponding to a position on a screen. For example, in a shooting game, when the trigger of a gun aimed at a TV screen is pulled, SDCKB is output by the gun. This SDCKB is used to identify the aim (shooting) position of the gun on the screen by means of the HV counter.

FIG. 22 is a circuit diagram illustrating the operational principles of the frame encoder 59. In this diagram, 591 is a flip-flop, 592 is a counter, 593 is a comparator and 594 is a logic gate.

FIG. 23 is a timing chart for describing the operation of the frame encoder 59.

When a write pulse is supplied to the frame encoder 59, this circuit assumes an active state. The SDCKA at output Q of the flip-flop 591 is set to level "L" by the rising edge of the write pulse. SDCKA forms an enable input to the counter 592, which starts a count of the clock CLK supplied thereto. The counter 592 advances a count value CNT OUT through "0", "1", "2", . . . "7", "8". This count value is supplied to comparison input A of the comparator 593. An output pattern set value n is supplied to the comparison reference input B of the comparator 593. For example, if a "start pattern" is generated, then the frame encoder 59 decodes this command and supplies "9" as a set value n. If the two inputs match, the comparator 593 outputs CMP OUT from output terminal EQ, which is supplied to preset terminal IPR of the flip-flop 591. Thereby, the SDCKA at output Q of the flip-flop 591 is set to level "H". SDCKB is obtained by synthesizing SDCKA and a CLKB signal having half the frequency of clock signal CLK at the OR gate 594.

In this way, output pattern set values corresponding to a start pattern, reset pattern and end pattern, etc. are supplied, and when a write pulse is input, the SDCKA is set to level "L", and for SDCKB a pattern signal having a prescribed umber of falling edges can be obtained.

FIG. 24 is a circuit diagram illustrating the operational principles of the alternate shift register 60. In this diagram, 601 is a shift register for converting parallel data to serial data; 602 is a dual-input selector; 603 is a shift register for converting parallel data to serial data; and 604 is a dual-input selector.

FIG. 25 is a timing chart describing the operation of the alternate shift register 60. A plurality of even-numbered bits D6, D4, D2, D0 for data transmission are supplied respectively to a plurality of D input terminals of the shift register 601, and the data is shifted by means of a shift clock SHIFT CLKA having the timing illustrated in the diagram, and it is supplied from output terminal Q to the A input terminal of the selector 602 as serial data. A clock CLKA as shown in the diagram is input to the B input terminal of the selector 602. The selector 602 selects the serial data from output terminal Q in accordance with level "H" of the shift clock SHIFT CLKA, and it selects clock CLKA in accordance with level "L" of SHIFT CLKA.

Therefore, an SDCKA signal, wherein data D6, D4, D2, D0 are superimposed on clock CLKA at prescribed intervals, is obtained at output terminal Y of the selector 602. Similarly, a plurality of odd-numbered bits D7, D5, D3, D1 for transmission are supplied respectively to a plurality of D input terminals of the shift register 603, and the data is shifted by means of a shift clock SHIFT CLKB having the timing illustrated in the diagram and supplied from output terminal Q to the A input terminal of the selector 604 as serial data. A clock CLKB as shown in the diagram is input to the B input terminal of the selector 604. The selector 604 selects the serial data from output terminal Q in accordance with level "H" of the shift clock SHIFT CLKB, and it selects clock CLKB in accordance with level "L" of SHIFT CLKA. Therefore, an SDCKB signal, wherein data D7, D5, D3, D1 are superimposed on clock CLKB at prescribed intervals, is obtained at output terminal Y of the selector 604. The sections "D0"-"D7" shown in signals SDCKA and SDCKB have a level "H" or a level "L" depending on their data value.

FIG. 26 is a circuit diagram showing a compositional example of a frame decoder 61. In this diagram, 611 is a counter, 612 is a composite flip-flop consisting of a plurality of flip-flops, 613 is a counter, and 614 is a composite flip-flop consisting of a plurality of flip-flops. FIG. 27 is a timing chart describing the operation of the frame decoder 61.

Of the elements in the diagram, the counter 611 and flip-flop 612 operate in the detection of a start pattern. When the SDCKA is at level "H", the counter operation is disabled. When SDCKA takes level "L", the counter operation is enabled, and the falling edges of SDCKB are counted. By counting the number of falling edges of SDCKB whilst SDCKA is at level "L", a count output is supplied to the flip-flop. The counter output is supplied to the flip-flop 612 at the rising edge of SDCKA.

As shown in FIG. 27, if the number of falling edges of the SDCKB is four during the period in which SDCKA is at "L" level (start pattern, cf. FIG. 13), flip-flop 612 outputs the start pattern detection.

For detecting the end pattern, the number of falling edges of the SDCKA whilst SDCKB is at "L" level is counted via the counter 613 and flip-flop 614. Through this rising edge of the SDCKB, the count output 613 is incorporated in the counter 613. As shown in FIG. 27, when two falling edges of the SDCKA are counted whilst SDCKB is at "L" level, the flip-flop 612 outputs the end pattern detection. When the number of falling edges of the SDCKA during the period in which the SDCKB is at "L" level is unspecified, the flip-flop 614 outputs a frame error detection. In the normal operation mode, the data pattern and the end with two falling edges of the SDCKA follow the start pattern with four falling edges of the SDCKB (cf. FIG. 11).

Furthermore, although not illustrated in FIG. 27, after commencement of the reception, when the counter 611 detects six falling edges of the SDCKB whilst SDCKA is at "L" level, the flip-flop 612 outputs the detection of a start pattern with CRC (FIG. 14). In the operation mode using the CRC, the data pattern, CRC data, and the end pattern follow the CRC start pattern with six falling edges of the SDCKB (cf. FIG. 12).

Furthermore, if the counter 611 detects the falling edges of the SDCKB eight times whilst SDCKA is at "L" level, then the flip-flop 612 outputs the detection of SDCKB occupancy permission pattern (cf. FIG. 15). When the pattern is detected, the operation mode shifts to the SDCKB occupancy permission operation mode. In the SDCKB occupancy permission operation mode, light-gun is useable. The SDCKB occupancy permission mode is reset by the SDCKB occupancy permission operation mode reset pattern (rising edge of the SDCKA).

If counter 611 detects the falling edges of the SDCKB fourteen times whilst SDCKA is at "L" level, the flip-flop 612 outputs the detection of reset pattern (cf. FIG. 16). The detection allows the reset operation.

If the number of falling edges of the SDCKB is unspecified, the flip-flop 612 outputs the detection of frame error. The pattern detection outputs from flip-flops 612 and 614 are held in status register 55.

FIG. 28 shows a compositional example of the alternate shift register 62. In this diagram, serial data SDCKB is supplied to the data input terminal D of a shift register 621, and SDCKA is supplied to the shift clock input thereof. The shift register 621 reads in the data sections of SDCKB successively at the falling edges of SDCKA, as illustrated in FIG. 29. Serial-to-parallel converted data is arranged at the parallel output terminals D7, D5, D3, D1 of the shift register 621 by four clock edges of SDCKA.

Similarly, serial data SDCKA shown in FIG. 29 is supplied to the data input terminal D of the shift register 622 shown in FIG. 28, and SDCKB is supplied to the shift clock input thereof. The shift register 622 reads in the data sections of SDCKA successively at the falling edges of SDCKB. Serial-to-parallel converted data is arranged at the parallel output terminals D6, D4, D2, D0 of the shift register 622 by four clock edges of SDCKB.

FIG. 30 is an approximate general block diagram of a peripheral device to be connected to a game device, generally called a game controller, an input operation controller, or an operation input device, etc. A game controller will be described below. It is possible to add (couple) further peripheral devices (L-device functions) by providing two expansion sockets on the game controller. The game controller contains a one-chip micro-controller. It also comprises 11 switches for generating digital output, and analogue keys for generating a four-axis output. The output of these switches, etc. is processed by the micro-controller, and output to the host via an MIE section and an M bus.

FIG. 31 is a block diagram giving an approximate illustration of the composition of an MIE on the device function side, where the functions of a peripheral device are taken as the device functions.

In this diagram, the game controller is connected to a host (omitted from drawing) via an M bus. The game controller comprises a U-device function connected to the host via the M bus, and two L-device functions connected to the U-device function via LM buses.

FIG. 32 is a block circuit diagram showing a bus switching section (selector) from FIG. 31. There are two M buses branching from the U-device function, and these are called LM bus 1 and LM bus 2, respectively. The switching operation to connect and disconnect the LM buses and M bus is performed by an MIE selector in the U-device function.

FIG. 33 is an approximate block diagram of a hardware section of the U-device function. The transmission processing section, socket control section, CPU section, and I/O section are constituted by a one-chip micro-controller. The transmission processing block forms an interface with the host. The CPU section controls the signal processing in the peripheral device, such as a game controller, or the like. The I/O section is an external input interface for digital buttons, analogue keys, or the like. The socket control section is used for controlling expansion sockets. In this example, hardware expansion sockets (two-slot) for two L-device functions are prepared.

FIG. 34 is an approximate block diagram of an L-device function. A transmission processing section, CPU section, and support function section are constituted by a single-chip microcomputer. The transmission processing section forms an interface with the U-device function (MIE for L-device function). The CPU section carries out processing relating to he L-device function. The support function block realizes the unction of the L-device function, for example, a circuit for performing the trigger function of a light gun, memory function, or vibrating function, etc.

Next, the operation of the MIE on the device function side is described with reference to FIGS. 33 and 34. In the initial state where APs are not allocated, a three-state buffer is controlled by the socket controller shown in FIG. 33, and SDCKA OUT and SDCKB OUT transmitted to expansion socket 1 and expansion socket 2 are disabled. Here, the socket controller performs the functions of an LM bus 1 controller and LM bus 2 controller.

With SDCKA OUT in a disabled state, when no L-device function is connected to the expansion socket,